Superconductor switches are capable of very high data rates with low power dissipation. Crossbar switches that are implemented using superconductor digital electronics are capable of high data rates per line and are reconfigurable within a few clock cycles. The crossbar switches also have a compact size of a few cubic centimeters and low on-chip power dissipation. Network routers and multiprocessor computers are a primary application of crossbar switches. For these applications, the crossbar switches must be self-routing. Using conventional crossbar switches in routers involves unacceptable overhead for the select logic. Conventional crossbar switches also need a parallel decoder circuit and an interconnect between the decoders and the crossbar switch. The row decoder also has one output connection for each column. In other words, each cross-point would need to be connected to its own decoder output.
While having high data rates, prior art superconductor switches have made compromises between data rate, power, scalability, total throughput, and reconfiguration time. Robert Sandell, John Spargo, and Michael Leung, “High Data Rate Switch With Amplifier Chip”, IEEE Trans. Appl. Supercond., vol. 9, pp. 2985-2988, (June 1999) discloses a switch that operates at 2.5 Gbps and performs self-routing. However, the switch has high decoder and interconnect overhead. Scalability and power dissipation can also be improved.
Qing Ke, Bruce Dalrymple, Dale Durand, and John Spargo, “Single Flux Quantum Crossbar Switch”, IEEE Trans. Appl. Supercond. vol. 7, pp. 2968-2971, (June 1997) discloses a switch that employs rapid single flux quantum (RSFQ) logic that enables ultra-high data rates but requires a parallel decoder. In addition, scalability and power dissipation are unacceptable.
L. Wittie, D. Zinoviev, G. Sazaklis, and K. Likharev, “CNET: Design of an RSFQ switching network for petaflops-scale computing,” IEEE Trans. Appl. Supercond., vol. 9, pp. 4034-4039, (June 1999) discloses a switch with a multi-stage Batcher-Baynan architecture that is implemented using RSFQ logic. Unfortunately, the switch has relatively high stage and interconnect complexity. Furthermore, the design has not been implemented.
S. Yorozu, Y. Hashimoto, H. Numata, S. Nagasawa, and S. Tahara, “System demonstration of a superconducting communication system,” IEEE Trans. Appl. Supercond., vol. 9, pp. 2975-2980, June 1999 discloses a switch that solves the interconnect problem by using a ring architecture. Potential throughput, however, does not compare favorably to crossbar switches.
In RSFQ logic, information is stored in superconductor loops as tiny magnetic flux quanta and a bit is transferred as several picosecond-wide voltage spike with a quantized area of approximately 2.07 mV ps. The tiny and quantized nature of magnetic flux quanta significantly (by several orders of magnitude) reduces crosstalk and power consumption as compared to CMOS devices.
The RSFQ circuit can be considered as consisting of elementary cells or timed gates. Each cell has two or more stable flux states. The cell is fed by SFQ input pulses S1, S2, . . . Si that can arrive from one or more signal lines and a clock timing line T. Each clock pulse marks a boundary between two adjacent clock periods by setting the cell into its initial state. During the new period, an SFQ pulse can arrive or not arrive at each of the cell inputs Si. Arrival of the SFQ pulse at a terminal Si during the current clock period defines the logic value 1 of the signal Si while the absence of the pulse during this period defines the logic value 0 of this signal.
RSFQ circuits do not require the exact coincidence of SFQ pulses in time nor is a specified time sequence of the various input signals needed. Each input pulse can either change or not change the internal state of the cell. Input pulses cannot produce an immediate reaction at the output terminal(s) Sout. Only the clock pulse T is able to fire out the pulse(s) Sout corresponding to the internal state of the cell predetermined by the input signal pulses that have arrived during the clock period. The same clock pulse terminates the clock period by resetting the cell into its initial state. An elementary cell of the RSFQ family is approximately equivalent to a typical asynchronous logic circuit coupled with a latch (flip-flop) that stores its output bit(s) until the end of the clock period.